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http://dx.doi.org/10.7471/ikeee.2018.22.1.104

Hardware Design and Implementation of Block Encryption Algorithm ARIA for High Throughput  

Yoo, Heung-Ryol (Dept. of Mechanical Facility Control Engineering, Korea University of Technology and Education)
Lee, Sun-Jong (Dept. of Mechanical Facility Control Engineering, Korea University of Technology and Education)
Son, Yung-Deug (Dept. of Mechanical Facility Control Engineering, Korea University of Technology and Education)
Publication Information
Journal of IKEEE / v.22, no.1, 2018 , pp. 104-109 More about this Journal
Abstract
This paper presents a hardware design for the block encryption algorithm of ARIA which is used for standard in Korea. It presents a hardware-efficient design to increase the throughput for the ARIA algorithm using a high-speed pipeline architecture. We have used ROM for the S-box implementation. This approach aims to decrease the critical path delay of the encryption. In this paper, hardware was designed by VHDL, realized RTL level by Synplify which is synthesis tool and verified simulation by ModelSim. The ARIA algorithm is shown 68.3 MHz (Maximum operation frequency) to use Xilinx VertxE XCV Series device.
Keywords
ARIA; Block Encryption Algorithm; Hardware; Pipeline; VHDL;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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