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http://dx.doi.org/10.7471/ikeee.2017.21.4.416

An Anti-Boundary Switching Digital Delay-Locked Loop  

Yoon, Junsub (Dept. of Electronic & Electrical Engineering, Hongik University)
Kim, Jongsun (Dept. of Electronic & Electrical Engineering, Hongik University)
Publication Information
Journal of IKEEE / v.21, no.4, 2017 , pp. 416-419 More about this Journal
Abstract
In this paper, we propose a new digital delay-locked loop (DLL) for high-speed DDR3/DDR4 SDRAMs. The proposed digital DLL adopts a fine delay line using phase interpolation to eliminate the jitter increase problem due to the boundary switching problem. In addition, the proposed digital DLL utilizes a new gradual search algorithm to eliminate the harmonic lock problem. The proposed digital DLL is designed with a 1.1 V, 38-nm CMOS DRAM process and has a frequency operating range of 0.25-2.0 GHz. It has a peak-to-peak jitter of 1.1 ps at 2.0 GHz and has a power consumption of about 13 mW.
Keywords
Delay-Locked Loop; DLL; Digital DLL; Boundary Switching; Harmonic lock; DDR3; DDR4; SDRAM;
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