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http://dx.doi.org/10.7471/ikeee.2016.20.4.435

Hardware Implementation of Binary Arithmetic Decoder in HEVC CABAC Decoder  

Kim, Sohyun (School of Electronic Engineering, Soongsil University)
Kim, Doohwan (School of Electronic Engineering, Soongsil University)
Lee, Seongsoo (School of Electronic Engineering, Soongsil University)
Publication Information
Journal of IKEEE / v.20, no.4, 2016 , pp. 435-438 More about this Journal
Abstract
HEVC CABAC binary arithmetic decoder operates in three decoding modes i.e. regular, bypass, and termination modes, where their decoding operations and time differ a lot. Furthermore, when renormalization occurs, its internal feedback loop induces large delay. In this paper, a binary arithmetic decoder was designed to solve this problem. In advance, it checks all range values with possible renormalization. When renormalization occurs, it immediately updates range value and finishes all calculation in a cycle. When implemented in 0.18 um process technology, its maximum operating frequency and gate counts are 215 MHz and 5,423 gates, respectively.
Keywords
HEVC; CABAC; Decoder; Binary Arithmetic Decoder; BAD;
Citations & Related Records
Times Cited By KSCI : 11  (Citation Analysis)
연도 인용수 순위
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