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http://dx.doi.org/10.7471/ikeee.2016.20.4.398

FPGA Implementation of SVM Engine for Training and Classification  

Na, Wonseob (Dept. of Electronics and Communications Engineering, Kwangwoon University)
Jeong, Yongjin (Dept. of Electronics and Communications Engineering, Kwangwoon University)
Publication Information
Journal of IKEEE / v.20, no.4, 2016 , pp. 398-411 More about this Journal
Abstract
SVM, a machine learning method, is widely used in image processing for it's excellent generalization performance. However, to add other data to the pre-trained data of the system, we need to train the entire system again. This procedure takes a lot of time, especially in embedded environment, and results in low performance of SVM. In this paper, we implemented an SVM trainer and classifier in an FPGA to solve this problem. We parlallelized the repeated operations inside SVM and modified the exponential operations of the kernel function to perform fixed point modelling. We implemented the proposed hardware on Xilinx ZC 706 evaluation board and used TSR algorithm to verify the FPGA result. It takes about 5 seconds for the proposed hardware to train 2,000 data samples and 16.54ms for classification for $1360{\times}800$ resolution in 100MHz frequency, respectively.
Keywords
Machine Learning; SVM; FPGA; Training; Classification;
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Times Cited By KSCI : 2  (Citation Analysis)
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