[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.7471/ikeee.2015.19.2.254

Hardware Implementation of HEVC CABAC Context Modeler

Kim, Doohwan (School of Electronic Engineering, Soongsil University)
Moon, Jeonhak (School of Electronic Engineering, Soongsil University)
Lee, Seongsoo (School of Electronic Engineering, Soongsil University)

Publication Information

Journal of IKEEE / v.19, no.2, 2015 , pp. 254-259 More about this Journal

Abstract

CABAC is a context-based adaptive binary arithmetic coding method. It increases the encoding efficiency by updating the probability based on the information of the previously coded symbols. Context modeler is a core block of CABAC, which designs a probability model according to the symbol considering statistical correlations. In this paper, an efficient hardware architecture of CABAC context modeler is proposed. The proposed context modeler was designed in Verilog HDL and it was implemented in 0.18 um technology. Its gate count is 29,832 gates including memory. Its operating speed and throughput are 200 MHz and 200 Mbin/s, respectively.

Keywords

HEVC; CABAC; context modeler; hardware; implementation;

Citations & Related Records

Times Cited By KSCI : 4 (Citation Analysis)

Reference
Cited By KSCI

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KSCI

Hardware Implementation of HEVC CABAC Context Modeler HEVC CABAC 문맥 모델러의 하드웨어 구현

Hardware Implementation of HEVC CABAC Context Modeler