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http://dx.doi.org/10.7471/ikeee.2015.19.1.041

Dielectric Layer Planarization Process for Silicon Trench Structure  

Cho, Il Hwan (Dept. of Electronic Engineering, Myongji University)
Seo, Dongsun (Dept. of Electronic Engineering, Myongji University)
Publication Information
Journal of IKEEE / v.19, no.1, 2015 , pp. 41-44 More about this Journal
Abstract
Silicon trench process for bulk fin field effect transistor (finFET) is suggested without using chemical mechanical polishing (CMP) that cause contamination problems with chemical stuff. This process uses thickness difference of photo resistor spin coating and silicon nitride sacrificial layer. Planarization of silicon oxide and silicon trench formation can be performed with etching processes. In this work 50 nm silicon trench is fabricated with AZ 1512 photo resistor and process results are introduced.
Keywords
bulk finFET; isolation; semiconductor; etching process; planarization;
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