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http://dx.doi.org/10.7471/ikeee.2015.19.1.001

Design of Sub-pixel Interpolation Circuit for Real-time Multi-decoder Supporting 4K-UHD Video Images  

Lee, Sujung (Dept. of Electronics Engineering, Hankuk University of Foreign Studies)
Cho, Kyeongsoon (Dept. of Electronics Engineering, Hankuk University of Foreign Studies)
Publication Information
Journal of IKEEE / v.19, no.1, 2015 , pp. 1-9 More about this Journal
Abstract
This paper proposes the design of sub-pixel interpolation circuit for real-time multi-decoder supporting 4K-UHD video images. The proposed sub-pixel interpolation circuit supports H.264, MPEG-4, VC-1 and new video compression standard HEVC. The common part of the interpolation algorithm used in each video compression standard is shared to reduce the circuit size. An intermediate buffer is effectively used to reduce the circuit size and optimize the performance. The proposed sub-pixel interpolation circuit was synthesised by using 130nm standard cell library. The synthesized gate-level circuit consists of 122,564 gates and processes 35~86 image frames per second for 4K-UHD video at the maximum operation frequency of 200MHz. Therefore, the proposed circuit can process 4K-UHD video in real time.
Keywords
low-area design; multi-decoder; sub-pixel interpolation; real-time processing; video compression;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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1 B. Bross, W. J. Han, J. R. Ohm, G. J. Sullivan, Y. K. Wang and T. Wiegand, "High Efficiency Video Coding (HEVC) Text Specification Draft 10 (for FDIS & Last Call)," The Joint Collaborative Team on Video Coding (JCT-VC), JCTVC-L1003_v34, January, 2013.
2 ITU-T, "Recommendation and International Standard of Joint Video Specification," ITU-T Recommendation H.264/ISO/IEC 14496-10 AVC, October, 2004.
3 ISO/IEC 14496-2, "Coding of Audio-Visual Objects - part 2: Visual," November, 1997.
4 SMPTE, Standards for Television: VC-1 Compressed Video Bitstream Format and Decoding Process, SMPTE 421M-2006.
5 X. Jin and K. Ryoo, "An Efficient Interpolation Hardware Architecture for HEVC Inter-Prediction Decoding," Journal of Information and Communication Convergence Engineering, vol.11, no.2, pp.118-123, June, 2013.   DOI
6 G. Lee, W. Yang, M. Wu and H. Lin, "Reconfigurable architecture design of motion compensation for multi-standard video coding," IEEE International Symposium on Circuits and Systems, pp.2003-2006, May, 2010.