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http://dx.doi.org/10.7471/ikeee.2014.18.4.630

Hardware Implementation of HEVC CABAC Binary Arithmetic Encoder  

Pham, Duyen Hai (School of Electronic Engineering, Soongsil University)
Moon, Jeonhak (School of Electronic Engineering, Soongsil University)
Kim, Doohwan (School of Electronic Engineering, Soongsil University)
Lee, Seongsoo (School of Electronic Engineering, Soongsil University)
Publication Information
Journal of IKEEE / v.18, no.4, 2014 , pp. 630-635 More about this Journal
Abstract
In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.
Keywords
HEVC; CABAC; binary arithmetic encoder; hardware; implementation;
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
연도 인용수 순위
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