Browse > Article
http://dx.doi.org/10.7471/ikeee.2013.17.4.511

Sigma-Delta Modulator using a novel FDPA(Feedback Delay Path Addition) Technique  

Jung, Eui-Hoon (Dept. of Electronics Engineering, Chonbuk University)
Kim, Jae-Bung (Dept. of Electronics Engineering, Chonbuk University)
Cho, Seong-Ik (Dept. of Electronics Engineering, Chonbuk University)
Publication Information
Journal of IKEEE / v.17, no.4, 2013 , pp. 511-516 More about this Journal
Abstract
This paper presents a SDM using the FDPA technique. The FDPA technique is the added feedback path which is the delayed path of DAC output. The designed SDM increases the SNR by adding the delayed digital feedback path. The proposed SDM is easily implemented by eliminating the analog feedback path. Through the MATLAB modeling, the optimized coefficients are obtained to design the SDM. The designed SDM has a power consumption of $220{\mu}W$ and SNR(signal to noise ratio) of 81dB at the signal-bandwidth of 20KHz and sampling frequency of 2.56MHz. The SDM is designed using the $0.18{\mu}m$ standard CMOS process.
Keywords
Sigma-Delta Modulator; Noise shaping; FDPA; Opamp Sharing; Non-overlapping clock;
Citations & Related Records
연도 인용수 순위
  • Reference
1 James C.Morizio, Michael Hoke, Taskin Kocak, Clark Geddie, Chris Hughes, John Perry, Srinadh Madhavapeddi, Michael H. Hood, George Lynch, Harufusa Kondoh, Toshio Kumamoto, Takashi Okuda, Hiroshi Noda, Masahiko Ishiwaki, Takahiro Miki, and Masao Nakaya "14-bit 2.2-MS/s Sigma-Delta ADC's," IEEE J. Solid-State Circuits, vol. 35, No. 7, pp. 968-976, July. 2000   DOI   ScienceOn
2 Daisuke Kanemoto, Toru Ido and Kenji Taniguchi, "A 7.5mW 101dB SNR Low-Power High-Performance Audio Delta-Sigma Modulator Utilizing Opamp Sharing Technique" SoC Design Conference(ISOCC), 2011 International, pp. 66-69. 2011.
3 Chuan-Hung Hsiao, Wei-Lin Chen, Chih-Cheng Hsieh , "A 0.8V 80.3dB SNDR Stage-Shared ${\Delta}{\Sigma}$ Moudulator with chopper-Embeded Switched-Opamp for Biomedical Application", IEEE Asian Solid-State Circuits Conference, IPEC.2012.6522673, pp. 253-256, 2012.
4 Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai, "Managing Subthreshold Leakage in Charge-BasedAnalog Circuits With Low-Vth Transistors by Analog TSwitch (AT-Switch) and Super Cut-off CMOS (SCCMOS), IEEE J. Solid-State Circuits, vol. 41, No. 4, pp. 859-867, Apr. 2006   DOI   ScienceOn
5 J. Koh, Y. Chio, and G. Gomez, "A 66dB DR 1.2V 1.2mW single-amplifier double-sampling 2nd-order ${\Delta}{\Sigma}$ ADC for WCDMA in 90nm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, vol. 1, pp. 170-171.
6 Chuc K. Thanh, Stephen H. Lewis, and Paul J. Hurst, "A Second-Order Double-Sampled Delta-Sigma Modulator Using Individual-Level Averaging" IEEE J . Solid-State Circuits, vol. 32, No. 8, pp. 1269-1273, Aug. 1997.   DOI   ScienceOn
7 Gun-Hee Yun. "Design of A Low-Power 12-Bit Sigma-Delta Modulator" Hanyang University. 2011.
8 David A. Johns, Ken Martin, "Analog Integrated circuit design", pp. 542-571. 1997