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S. H. Shin, J. M. Choi, S. Cho, and K. S. Min, "Small-area and compact CMOS emulator circuit for memristors," submitted to Nano Research Letters, 2013.
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D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, "The missing memristor found," Nature, vol. 453, pp. 80-83, May 2008.
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D. Ventra, Y. V. Pershin, and L. O. Chua, "Circuit elements with memory: memristors, memcapacitors, and meminductors," Proceedings of the IEEE, vol. 97, no. 10, pp. 1717-1724, Oct. 2009.
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K. H. Jo, C. M. Jung, K. S. Min, and S. M. Kang, "Self-adaptive write circuit for low-power and variation-tolerant memristors," IEEE Trans. Nanotechnology, vol. 9, no. 6, pp. 675-678, Nov. 2010.
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C. M. Jung, J. M. Choi, and K. S. Min, "Two-step write scheme for reducing sneak-path leakage in complementary memristor array," IEEE Trans. Nanotechnology, vol. 11, no. 3, pp. 611-618, May 2012.
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O. Kwon and K. S. Min, "Dataline redundancy circuit using simple shift logic circuit for dual-port 1T-SRAM embedded in display ICs," Journal of Institute of Korean Electrical and Electronics Engineers, vol. 11, no. 4, pp. 129-136, Dec. 2007.
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Y. V. Pershin and D. Ventra, "Practical approach to programmable analog circuit with memristors," IEEE. Trans. Circuits and Systems, vol. 57, no. 8, pp. 1857-1864, Aug. 2010.
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C. M. Jung, K. H. Jo, and K. S. Min, "SPICE macromodel and CMOS emulator for memristors," Journal of Nanoscience and Nanotechnology, vol. 12, no. 2, pp. 1487-1491, Feb. 2012.
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H. Kim, M. Sah, C. Yang, S. Cho, and L. O. Chua, "Memristor emulator for memristor circuit applications," IEEE Trans. Circuits and Systems, vol. 59, no. 10, pp. 2422-2431, Oct. 2012.
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J. M. Choi, S. H. Shin, S. Cho, and K. S. Min, "CMOS circuit with small area and low complexity for emulation memristive behavior," Collaborate Conference on 3D & Material Research (CC3DMR), Jeju in Korea, June 2013.
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C. M. Jung, E. S. Lee, and K. S. Min, "Continuous and accurate PCRAM current-voltage model," Journal of Semiconductor Technology and Science, vol. 11, no. 3, pp. 162-168, Sep. 2011.
과학기술학회마을
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T. Tanzawa, Y. Takano, K. Watanabe, and S. Atsumi, "High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing nor flash memories," IEEE Journal of Solid-State Circuits, vol. 37, no. 10, pp. 1318-1325, Oct. 2002.
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S. H. Lim and K. H. Park, "An efficient NAND flash file system for flash memory storage," IEEE Trans. Computers, vol. 55, no. 7, pp. 906-912, July 2006.
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S. Kuge, F. Morishita, T. Tsuruda, S. Tomishima, M. Tsukude, T. Yamagata, and K. Arimoto, "SOI-DRAM circuit technologies for low power high speed multigiga scale memories," IEEE Journal of Solid-State Circuits, vol. 31, no. 4, pp. 586-591, Apr. 1996.
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A. Driskill-Smith, D. Apalkov, V. Nikitin, X. Tang, S. Watts, D. Lottis, K. Moon, A. Khvalkovskiy, R. Kawakami, X. Luo, A. Ong, E. Chen, and M. Krounbi, "Latest advances and roadmap for in-plane and perpendicular STT-RAM," IEEE International Memory Workshop, pp. 1-3, Monterey in California, May 2011.
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X. Q. Wei, L. P. Shi, R. Walia, T. C. Chong, R. Zhao, X. S. Miao, and B. S. Quek, "HSPICE macromodel of PCRAM for binary and multilevel storage," IEEE Trans. Electron Devices, vol. 53, no. 1, pp. 56-62, Jan. 2006.
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S. Tehrani, J. M. Slaughter, E. Chen, M. Durlam, J. Shi, and M. DeHerrera, "Progress and outlook for MRAM technology," IEEE Trans. Magnetics, vol. 35, no. 5, pp. 2814-2819, Sep. 1999.
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