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http://dx.doi.org/10.7471/ikeee.2013.17.3.275

A 8-bit 10-MSample/s Folding & Interpolation ADC using Preamplifier Sharing Method  

Ahn, Cheol-Min (Department of Information Technology Handong Global University)
Kim, Young-Sik (Department of Information Technology Handong Global University)
Publication Information
Journal of IKEEE / v.17, no.3, 2013 , pp. 275-283 More about this Journal
Abstract
In this paper, a 8bit 10Ms/s CMOS Folding and Interpolation analog-to-digital convertor is proposed. The architecture of the proposed ADC is based on a Folding & Interpolation using FR(Folding Rate)=8, NFB(Number of Folding Block)=4, IR(Interpolation Rate)=8. The proposed ADC adopts a preamplifier sharing method to decrease the number of preamplifier by half comparing to the conventional ones. This chip has been fabricated with a 0.35[um] CMOS technology. The effective chip area is $1.8[mm]{\times}2.11[mm]$ and it consumes 20[mA] at 3.3 power supply with 10[MHz] clock. The INL is -0.57, +0.61 [LSB] and DNL is -0.4, +0.51 [LSB]. The SFDR is 48.9[dB] and SNDR is 47.9[dB](ENOB 7.6b) when the input frequency is 100[kHz] at 10[MHz] conversion rate.
Keywords
ADC; Folding; Interpolation; Zero-Crossing; Thermometer-Encoder; SFDR;
Citations & Related Records
Times Cited By KSCI : 5  (Citation Analysis)
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