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http://dx.doi.org/10.7471/ikeee.2013.17.3.260

The noise impacts of the open bit line and noise improvement technique for DRAM  

Lee, Joong-Ho (Dept. of Computer Science, Yongin University)
Publication Information
Journal of IKEEE / v.17, no.3, 2013 , pp. 260-266 More about this Journal
Abstract
The open bit line is vulnerable to noise compared to the folded bit line when read/write for the DRAM. According to the increasing DRAM densities, the core circuit operating conditions is exacerbated by the noise when it comes to the open bit line 6F2(F : Feature Size) structure. In this paper, the interference effects were analyzed by the data patterns between the bit line by experiments. It was beyond the scope of existing research. 68nm Tech. 1Gb DDR2, Advan Tester used in the experiments. The noise effects appears the degrade of internal operation margin of DRAM. This paper investigates sense amplifier power line splits by experiments. The noise can be improved by 0.2ns(1.3%)~1.9ns(12.7%), when the sense amplifier power lines split. It was simulated by 68nm Technology 1Gb DDR2 modeling.
Keywords
$6F^2$; open bit line; data pattern interference effects; adjacent bit line; sense amplifier power line splits;
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