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http://dx.doi.org/10.7471/ikeee.2013.17.2.202

FPGA based Implementation of FAST and BRIEF algorithm for Object Recognition  

Heo, Hoon (Dept. of Computer Enginerring, Seokyeong University)
Lee, Kwang-Yeob (Dept. of Computer Enginerring, Seokyeong University)
Publication Information
Journal of IKEEE / v.17, no.2, 2013 , pp. 202-207 More about this Journal
Abstract
This paper implemented the conventional FAST and BRIEF algorithm as hardware on Zynq-7000 SoC Platform. Previous feature-based hardware accelerator is mostly implemented using the SIFT or SURF algorithm, but it requires excessive internal memory and hardware cost. The proposed FAST & BRIEF accelerator reduces approximately 57% of internal memory usage and 70% of hardware cost compared to the conventional SIFT or SURF accelerator, and it processes 0.17 pixel per Clock.
Keywords
FAST; BRIEF; Hamming Distance; SURF; SIFT;
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