1 |
M. Nazm Bojnordi, E. Ipek, "Programmable DDRx Controllers", IEEE Micro, Early access, accepted for publishing, 2013
|
2 |
H.-W. Lee, H. Choi, B.-J. Shin, K.-H. Kim, K.-W. Kim, J. Kim, K.-H. Kim, J.-H. Jung, J.-H. Kim, E.-Y. Park, J.-S. Kim, J.-H. Kim, J.-H. Cho, N. Rye, J.-H. Chun, Y. Kim, C. Kim, Y.-J. Choi, B.-T. Chung, "A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces," IEEE Journal of Solid-State Circuits, Vol. 47(6), pp. 1436-1447, 2012
DOI
ScienceOn
|
3 |
http://www.uniquify.com
|
4 |
Double Data Rate (DDR) SDRAM, JEDEC Standard, Feb. 2008.
|
5 |
DDR2 SDRAM SPECIFICATION, JEDEC Standard, Nov. 2009
|
6 |
DDR3 SDRAM SPECIFICATION, JEDEC Standard, Jul. 2010
|
7 |
Engin Ipek, Onur Mutlu, Jose F. Martınez, Rich Caruana1, "Self-Optimizing Memory Controllers: A Reinforcement Learning Approach", 35th International Symposium on Computer Architecture, 2008.(ISCA '08), pp. 39-50, June 21-25, 2008, Beijing, China
|
8 |
Jose Carlos Sancho, Michael Lang, Darren J. Kerbyson, "Analyzing the Trade-off between Multiple Memory Controllers and Memory Channels on Multi-core Processor Performance", 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), pp. 1-7, Apr. 19-23, 2010, Atlanta, USA
|
9 |
Vijay Gaikwad, Shashikant Lokhande, "An improved lane departure method for Advanced Driver Assistance System", 2011 International Conference on Electronics, Communications and Control (ICECC), pp. 372-375, Sep. 9-11, 2011, Ningbo, China
|
10 |
E. Herrero, J. Gonzalez, R. Canal, D. Tullsen, "Thread Row Buffers: Improving Memory Performance Isolation and Throughput in Multiprogrammed Environments", IEEE Transactions on Computers, Early access, accepted for publishing, 2012
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