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http://dx.doi.org/10.7471/ikeee.2012.16.4.343

Design of a Algorithmic ADC for Digital PFC Controller  

Jang, Ki-Chang (School of Electrical and Computer Engineering. University of Seoul)
Kim, Jin-Yong (School of Electrical and Computer Engineering. University of Seoul)
Hwang, Sang-Hoon (Samsung Electro-Mechanics Co., ltd.)
Choi, Joong-Ho (School of Electrical and Computer Engineering. University of Seoul)
Publication Information
Journal of IKEEE / v.16, no.4, 2012 , pp. 343-348 More about this Journal
Abstract
A 11b 100KS/s Algorithmic ADC for Digital PFC controller is proposed. The proposed Algorithmic ADC structure for 11bit resolution is based on a cyclic architecture to reduce chip area and power consumption. The prototype Algorithmic ADC implemented with a 0.18um 1Poly-3Metal CMOS process shows a SNDR 66.7dB and ENOB 10.78bits. And the current consumption is about 780uA at 100KS/s and 5V. The occupied active die area is $0.27mm^2$.
Keywords
Digital PFC Control; PFC; Algorithmic ADC; Algorithmic; Algorithmic ADC structure;
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Times Cited By KSCI : 1  (Citation Analysis)
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