1 |
Tsai, M.-C., Wang, T.-C., and Hwang, T. T., "Through-Silicon Via Planning in 3-D Floorplanning", Very Large Scale Integration (VLSI ) Systems, IEEE Transactions on vol.PP, no.99, pp.1-10, 2010
|
2 |
Healy, Michael B., and Lim, S.-K., "Power delivery system architecture for many-tier 3D systems", Components and Technology Conference (ECTC), 2010 Proceedings 60th, pp.1682-1688, 2010
|
3 |
Jung, M.-G., and Lim, S.-K., "A study of IR-drop noise issues in 3D ICs with Through-Silicon-Vias", IEEE International 3D System Integration Conference, pp.1-7, 2010
|
4 |
Hung, W.-L., Link, G., Xie Y., Vijaykrishnan, N., Irwin, M. J., "Interconnect and Thermal-aware Floorplanning for 3D Microprocessors", Proceedings of International Symposium on Quality Electronic Design (ISQED) , pp. 98-104, 2006
|
5 |
Jang, M.-S., Design Technology team, System LSI, Samsung Electronics Co., LTD, Private Communication
|