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http://dx.doi.org/10.7471/ikeee.2012.16.1.045

Power/Clock Network-Aware Routing Congestion Estimation Methodology at Early Design Stage  

Ahn, Byung-Gyu (Dept. of Electronics and Computer Engineering, Hanyang University)
Chong, Jong-Wha (Dept. of Electronics and Computer Engineering, Hanyang University)
Publication Information
Journal of IKEEE / v.16, no.1, 2012 , pp. 45-50 More about this Journal
Abstract
This paper proposes the methodology to estimate the routing congestion of modern IC quickly and accurately at the early stage of the design flow. The occurrence of over-congestion in the routing process causes routing failure which then takes unnecessary time to re-design the physical design from the beginning. The precise estimation of routing congestion at the early design stage leads to a successful physical design that minimizes over-congestion which in turn reduces the total design time cost. The proposed estimation method at the block-level floorplan stage measures accurate routing congestion by using the analyzed virtual interconnections of inter/intra blocks, synthesized virtual power/ground and clock networks.
Keywords
Routing congestion; Design methodology; Floorplan; EDA;
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