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http://dx.doi.org/10.7471/ikeee.2011.15.2.134

Design of a Tripple-Mode DC-DC Buck Converter  

Yu, Seong-Mok (Dept. of Electronics Engineering, University of Incheon)
Park, Joon-Ho (Dept. of Electronics Engineering, University of Incheon)
Park, Jong-Tae (Dept. of Electronics Engineering, University of Incheon)
Yu, Chong-Gun (Dept. of Electronics Engineering, University of Incheon)
Publication Information
Journal of IKEEE / v.15, no.2, 2011 , pp. 134-142 More about this Journal
Abstract
This paper describes a tripple-mode high-efficiency DC-DC buck converter. The DC-DC buck converter operate in PWM(Pulse Width Modulation) mode at moderate to heavy loads(100mA~500mA), in PFM(Pulse Frequency Modulation)at light loads(1mA~100mA), and in LDO(Low Drop Out) mode at the sleep mode(<1mA). In PFM mode DPSS(Dynamic Partial Shutdown Strategy) is also employed to increase the efficiency at light loads. The triple-mode converter can thus achieve high efficiencies over wide load current range. The proposed DC-DC converter is designed in a CMOS 0.18um technology. It has a maximum power efficiency of 96.4% and maximum output current of 500mA. The input and output voltages are 3.3V and 2.5V, respectively. The chip size is 1.15mm ${\times}$ 1.10mm including pads.
Keywords
DC-DC Converter; PWM; PFM; LDO; DPSS;
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