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A Link Layer Design for DisplayPort Interface  

Jin, Hyun-Bae (School of Electronics Engineering, Inha University)
Yoon, Kwang-Hee (Silicon Works Co., Ltd.)
Kim, Tae-Ho (School of Electronics Engineering, Inha University)
Jang, Ji-Hoon (School of Electronics Engineering, Inha University)
Song, Byung-Cheol (School of Electronics Engineering, Inha University)
Kang, Jin-Ku (School of Electronics Engineering, Inha University)
Publication Information
Journal of IKEEE / v.14, no.4, 2010 , pp. 297-304 More about this Journal
Abstract
This paper presents a link layer design of DisplayPort interface with a state machine based on packet processing. The DisplayPort link layer provides isochronous video/audio transport service, link service, and device service. The merged video, audio main link, and AUX channel controller are implemented with 7,648 LUTs(Loop Up Tables), 6020 register, and 821,760 of block memory bits synthesized using a FPGA board and it operates at 203.32MHz.
Keywords
DisplayPort; Main Link; Auxiliary channel (AUX channel); DisplayPort Configuration Data(DPCD); Extended Display Identification Data(EDID); Digital Visual Interface(DVI);
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  • Reference
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2 VESA, "DisplayPort Link Layer Compliance Test Standard", Version 1.0, September 14, 2007.
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4 IEC, Digital Audio Interface - part1 : general, IEC 60958-1, September 2008.
5 IEC, Digital Audio Interface - part3 : Consumer application, IEC 60958-3, May 2006.