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Differential Capacitor-Coupled Successive Approximation ADC  

Yang, Soo-Yeol (School of Electrical Engineering, Kookmin University)
Mo, Hyun-Sun (School of Electrical Engineering, Kookmin University)
Kim, Dae-Jeong (School of Electrical Engineering, Kookmin University)
Publication Information
Journal of IKEEE / v.14, no.1, 2010 , pp. 8-16 More about this Journal
Abstract
This paper presents a design of the successive approximation ADC(SA-ADC) applicable to a midium-low speed analog-front end(AFE) for the maximum 15MS/s CCD image processing. SA-ADC is effective in applications ranging widely between low and mid data rates due to the large power scaling effect on the operating frequency variations in some other way of pipelined ADCs. The proposed design exhibits some distinctive features. The "differential capacitor-coupling scheme" segregates the input sampling behavior from the sub-DAC incorporating the differential input and the sub-DAC output, which prominently reduces the loading throughout the signal path. Determining the MSB(sign bit) from the held input data in advance of the data conversion period, a kind of the signed successive approximation, leads to the reduction of the sub-DAC hardware overhead by 1 bit and the conversion period by 1 cycle. Characterizing the proposed design in a 3.3 V $0.35-{\mu}m$ CMOS process by Spectre simulations verified its validity of the application to CCD analog front-ends.
Keywords
SHA; SAR; SA-ADC; CCD analog-front end;
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