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A 2.7Gbps & 1.62Gbps Dual-Mode Clock and Data Recovery for DisplayPort in $0.18{\mu}m$ CMOS  

Lee, Seung-Won (Samsung Electronics co.)
Kim, Tae-Ho (School of Electronics Engineering, Inha University)
Lee, Suk-Won (Samsung Electronics co.)
Kang, Jin-Ku (School of Electronics Engineering, Inha University)
Publication Information
Journal of IKEEE / v.14, no.1, 2010 , pp. 40-46 More about this Journal
Abstract
This paper describes a clock and data recovery (CDR) circuit that supports dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a "Mode" switch control. The chip has been implemented using $0.18{\mu}m$ CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.
Keywords
clock and data recovery(CDR); voltage-controlled oscillator(VCO); DisplayPort; half-rate PD;
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  • Reference
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