1 |
K. Yamaguchi, et al., "12Gb/s Duobinary Signaling with x2 Oversampled Edge Equalization," IEEE ISSCC Dig. Of Tech. Papers, vol.1, pp.70-585, February 2005.
|
2 |
J. Buckwalter and A. Hajimiri, "A 10Gb/s Data-Dependent Jitter Equalizer," IEEE Custom Integrated Circuits Conference, pp.39-42, October 2004.
|
3 |
G, Zhang, P. Chaudhari, M. M. Green, "A BiCMOS 10Gb/s Adaptive Cable Equalizer," IEEE ISSCC Dig. Of Tech. Papers, vol.1, pp.482-541,February 2004.
|
4 |
G. Giustolisi, G. Palmisano, G. Palumbo, "A novel CMOS voltage Squarer," IEEE International Symposium on Circuits and Systems, pp.253-256, June 1997.
|
5 |
J. S. Choi, M. S. Hwang, D. K. Jeong, "A 0.18- CMOS 3.5-Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Control Method," IEEE JSSC, vol.39, pp. 419-425, March 2004.
|
6 |
S. Gondi, Equalization and Clock and Data Recovery Techniques for Serial-Link Receivers, Ph.D. dissertation, UCLA, LA, CA, 2006.
|
7 |
S. Gondi, B. Razavi, "Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers," IEEE JSSC, vol.42, pp.1999- 2011, September 2007.
|
8 |
Y. S. Sohn, S. J. Bae, H. J. Park, S. I. Cho, " A Decision Feedback Equalization Receiver for the STL SDRAM Interface with Clock-Date Skew compensation," IEICE Trans, vol.E87, May 2004.
|
9 |
J. Lee, "A 20-Gb/s Adaptive Equalizer in 0.13- CMOS Technology," IEEE ISSCC Dig. Of Tech. Papers, pp.273-282, February 2006.
|
10 |
S. Gondi, J. Lee, K. Takeuchi, B. Razavi, "A 10Gb/s CMOS Adaptive Equalizer for Backplane Applications," IEEE ISSCC Dig. Of Tech. Papers, vol.1, pp.328-601, February 2005.
|
11 |
A. C. Carusone, "Jitter Equalization for Binary Baseband Communication," IEEE International Symposium on Circuits and Systems, vol.2, pp.936-939, May 2005.
|
12 |
R. Payne, et al., "A 6.25-Gb/s Binary Transceiver in 0.13- CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels," IEEE JSSC, vol.40, pp.2646-2657, December 2005.
|