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A 5-Gb/s Continuous-Time Adaptive Equalizer  

Kim, Tae-Ho (School of Electronics Engineering, Inha University)
Kim, Sang-Ho (School of Electronics Engineering, Inha University)
Kang, Jin-Ku (School of Electronics Engineering, Inha University)
Publication Information
Journal of IKEEE / v.14, no.1, 2010 , pp. 33-39 More about this Journal
Abstract
In this paper, a 5Gb/s receiver with an adaptive equalizer for serial link interfaces is proposed. For effective gain control, a least-mean-square (LMS) algorithm was implemented with two internal signals of slicers instead of output node of an equalizing filter. The scheme does not affect on a bandwidth of the equalizing filter. It also can be implemented without passive filter and it saves chip area and power consumption since two internal signals of slicers have a similar DC magnitude. The proposed adaptive equalizer can compensate up to 25dB and operate in various environments, which are 15m shield-twisted pair (STP) cable for DisplayPort and FR-4 traces for backplane. This work is implemented in $0.18-{\mu}m$ 1-poly 4-metal CMOS technology and occupies $200{\times}300{\mu}m^2$. Measurement results show only 6mW small power consumption and 2Gbps operating range with fabricated chip. The equalizer is expected to satisfy up to 5Gbps operating range if stable varactor(RF) is supported by foundry process.
Keywords
Adaptive equalizer; Feed-Forward equalizer; DisplayPort; CDR; LMS algorithm;
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