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Peak Power Minimization for Clustered VLIW Architectures  

서재원 (한국과학기술원 전자전산학과)
김태환 (한국과학기술원 전자전산학과)
정기석 (홍익대학교 컴퓨터공학과)
Publication Information
Journal of KIISE:Computer Systems and Theory / v.30, no.5_6, 2003 , pp. 258-264 More about this Journal
Abstract
VLIW architecture has emerged as one of the most effective architectures in dealing with multimedia applications. In multimedia applications, there is ample potential for parallelizing the execution of multiple operations because such applications typically have data intensive processing which often has limited data and/or control dependencies. As the degree of instruction-level parallelism increases, non-clustered VLIW architectures scale poorly because of the tremendous register port pressure. Therefore, clustered VLIW architecture is definitely preferred over non-clustered VLIW architecture when a higher degree of parallelizing is possible as in the case of multimedia processing However, having multiple clusters in an architecture implies that the amount of hardware is quite large, and therefore, power consumption becomes a very crucial issue. In this paper, we propose an algorithm to minimize the peak power consumption without incurring little or no delay penalty. The effectiveness of our algorithm has been verified by various sets of experiments, and up to 30.7% reduction in the peak power consumption is observed compared with the results that is optimized to minimize resources only.
Keywords
VLIW; VLIW; peak power; scheduling;
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