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An Automatic Simulation Technique for UML State Machine Diagrams based on Abstract Scenarios in Sequence Diagrams  

Guo, Hui (경북대학교 전자전기컴퓨터학부)
Lee, Woo-Jin (경북대학교 전자전기컴퓨터학부)
Publication Information
Journal of KIISE:Software and Applications / v.36, no.6, 2009 , pp. 443-450 More about this Journal
Abstract
In an earlier development phase, the simulation technique is one of the key analysis methods for checking the correctness of system's functional requirements. In general, simulation is manually or randomly performed by executing state machine diagrams according to the requirement scenarios. Therefore, simulation is one of the most effort-consuming tasks. In this paper, an automatic simulation technique of state machine diagrams is provided according to the scenarios of the sequence diagrams. It is not easy to generate detailed simulation traces from sequence diagrams due to different abstraction levels between sequence diagrams and state machine diagrams. In order to adjust for different abstraction levels, state machine diagrams and sequence diagrams are transformed into LTS models and compositional analysis and transition reduction are performed. After checking behavior conformance between them, detailed simulation traces for the state machine diagrams are generated. These simulation traces are used not only for performing automatic simulation but also for assisting analyzers to reach a specific system state in order to guide further efficient simulation.
Keywords
simulation; sequence diagram; state machine diagram; LTS; UML;
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