Browse > Article

매니 코어 기반 패킷 프로세서 디자인  

Song, Yong-Un (서강대학교)
Lee, Hyeok-Jun (서강대학교)
Publication Information
Communications of the Korean Institute of Information Scientists and Engineers / v.32, no.5, 2014 , pp. 42-50 More about this Journal
Keywords
Citations & Related Records
연도 인용수 순위
  • Reference
1 C. Celio, "Cache Coherency Strategies in a Many-core Processor," Master Dissertation, MIT, 2009
2 K. Karras, D. Llorente, T. Wild, and A. Herkersdorf, "Improving Memory Subsystem Performance in Network Processors with Smart Packet Segmentation," Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, pp. 210-217, July 2008
3 H.-J. Lee, and E.-Y. Chung, "Scalable QoS-aware Memory Controller for High-Performance Packet Memory", IEEE transactions on VLSI Systems, Vol. 16, Issue 3, 2008
4 M. Martin, M. Hill, and D. Sorin, "Why on-chip cache coherency is here to stay," Communications of the ACM, Vol. 55, Issue 7, pp. 78-89, 2012
5 M. Herlihy and J. Moss, "Transactional Memory: Architectural Support for Lock-free Data Structures," Proceedings of the 20th International Symposium on Computer Architecture, pp. 289-300. 1993
6 L. Hammond, V. Wong, M. Chen, B. Carlstrom, J. Davis, B. Hertzberg, M. Prabhu, H. Wijaya; C. Kozyrakis, K. Olukotun, "Transactional memory coherency and consistency." Proceedings of the 31st annual International Symposium on Computer Architecture, pp. 102-13, 2004
7 K. Moore, J. Bobba, M. Moravan, M. Hill, and D. Wood, "LogTM: Log-based Transactional Memory," Proceedings of The Twelfth International Symposium on High-Performance Computer Architecture, pp. 254- 265, 2006
8 J. Chen, A Nair, and L. John, "Predictive hetrogeneityaware application scheduling for CMP," IEEE Transactions on Computers, http://doi.ieeecomputersociety. org/10.1109/TC.2012.212
9 Q. Wu, and T. Wolf, "Dynamic Workload Profiling and Task Allocation in Packet Processing Systems," IEEE International Conference on High Performance Switching and Routing, pp. 123-130, May 2008
10 V. Ramamurthi, J. McCollum, C. Ostler, and K. Chatha, "System Level Methodology for Programming CMP based Multi-threaded Network Processor Architecture," Proceedings of IEEE Computer Society Annual Symposium on VLSI, 2005
11 T. Wolf, and M. Flanklin, "Performance Models for Network Processor Design," IEEE Transactions on Parallel and Distributed Systems, Vol. 17, No. 6, June 2006
12 X. Huang, and T. Wolf, "Evaluating Dynamic Task Mapping in Network Processor Runtime Systems," IEEE Transactions on Parallel and Distributed Systems, Vol 19, No. 8, Aug., 2008
13 W. Shi, M. MacGregor, and P. Gburzynski, "Load Balancing for Parallel Forwarding," IEEE Transactions on Networking, Vol 13, No. 4, Aug. 2005
14 H. Liu, "Routing Prefix Caching in Network Processor Design," International Conference on Computer Communications and Networks, pp. 18-23, 2001
15 L. Yang, T. Gohad, P. Ghosh, D. Sinha, A. Sen, and A. Richa, "Resource Mapping and Scheduling for Hetrogeneous Network Processor Systems," Proceedings of IEEE/ACM symposium on Architectures for Networking and Communications Systems, Oct. 2005
16 P. Ienne, and R. Leupers, "Customizable Embedded Processors: Design Technologies and Applications," Morgan Kaufmann, 2006
17 J. Mudigonda, H. Vin, R. Yavatkar, "Overcoming the Memory Wall in Packet Processing: Hammers or Ladders?," Proceedings of IEEE/ACM symposium on Architectures for Networking and Communications Systems, Oct. 2005
18 H.-J. Lee, W.-C. Cho, and E.-Y. Chung, "Analytical Memory Bandwidth Model for Many-core Processor Based Systems," IEICE Electronics Express, Vol.9, No.18, pp. 1461-1466, 2012   DOI   ScienceOn
19 J. Hassan, S. Chandra, and T. Vijaykumar, "Efficient Use of Memory Bandwidth to Improve Network Processor Throughput," Proceedings of International Symposium on Computer Architecture, 2003
20 G. Kornaros, I. Papaefstathiou, A. Nikologiannis, N. Zervos, "A Fully-Programmable Memory Management System Optimizing Queue Handling at Multi Gigabit Rates," Proceedings of DAC, June, 2003
21 Cisco QuantumFlow Processor: Cisco's Next Generation Network Processor, http://www.cisco.com/en/ US/prod/collateral/routers/ps9343/solution_overview_ c22-448936.pdf
22 A. Garrett, G. Drenan, C. Morris, "Juniper Networks$((R))$ Field Guide and Reference," Addison-Wesley Professional, 2002
23 J. Allen, B. Bass, C. Basso, R. Boivie, J. Calvignac, G.Davis, L.Frelechoux, M.Heddes, A. Herkersdorf, A. kind, J. Logan, M. Peyravian, M. Rinaldi, R. Sabhikhi, M.Siegel, M.Waldvogel, "IBM PowerNP network processor: Hardware, Software, and applications," IBM Journal of Research and Development, Vol. 47, pp.177- 194, 2003   DOI
24 B. Kil, and L. John, "NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors," Proceedings of International Conference on Computer Design, 2003
25 H. Liu, "A Trace Driven Study of Packet Level Parallelism," Proceedings of IEEE International Conference on Communications, pp.2191-2195, 2002
26 T. Wolf, and M. Flanklin, "CommBench-A Telecom munications Benchmark For Network Processors," Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software, April, 2000
27 G. Memik, W. Mangione-Smith, and W. Hu, "NetBench: A Benchmarking Suite for Network Processors," Proceedings of International Conference on Computer Aided Design, 2001
28 K. Papagiannaki, S. Moon, C. Fraleigh, P. Thiran, F. Tobagi, C. Diot, "Analysis of Measured Single-Hop Delay from an Operational Backbone Network," Proceedings of IEEE INFOCOM June 2002
29 K. Yi, and J. Gaudiot, "Network Applications on Simultaneous Multithreading Processors," IEEE Transactions on Computers, Vol 59, No. 9, Sept., 2010
30 F. Khunjush, M. El-Kharahi, K. Li, and N. Dimopoulos, "Network Processor Design Issues and Challenges", Proceedings on IEEE Pacific Rim Conference of Communications, Computers and signal Processing, 2003.
31 J. Carlstrom, and T. Boden, "Synchronous Dataflow Architecture for Network Processors," IEEE Micro, Vol. 24, Issue 5, pp.10-18, 2004