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http://dx.doi.org/10.3745/KTCCS.2021.10.9.235

Data Scrambling Scheme that Controls Code Density with Data Occurrence Frequency  

Hyun, Choulseung (서울시립대학교 컴퓨터과학부)
Jeong, Gwanil (서울시립대학교 컴퓨터과학부)
You, Soowon (서울시립대학교 컴퓨터과학부)
Lee, Donghee (서울시립대학교 컴퓨터과학부)
Publication Information
KIPS Transactions on Computer and Communication Systems / v.10, no.9, 2021 , pp. 235-242 More about this Journal
Abstract
Most data scrambling schemes generate pure random codes. Unlike these schemes, we propose a variable density scrambling scheme (VDSC) that differentiates densities of generated codes. First, we describe conditions and methods to translate plain codes to cipher codes with different densities. Then we apply the VDSC to flash memory such that preferred cell states occur more than others. To restrain error rate, specifically, the VDSC controls code densities so as to increase the ratio of center state among all possible cell states in flash memory. Scrambling experiments of data in Windows and Linux systems show that the VDSC increases the ratio of cells having near-center states in flash memory.
Keywords
Cell State; Data Scrambling; Flash Memory; Variable Density;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 N. Sommer, M. Anholt, O. Golov, U. Perlmutter, S. Winter, and G. Semo, "Data scrambling schemes for memory devices," US Patent (US 8,261,159 B1), 2012.
2 S. Tanakamaru, C. Hung, and K. Takeuchi, "Highly reliable and low power SSD using asymmetric coding and stripe bitline-pattern elimination programming," IEEE Journal of Solid-State Circuits, Vol.47, No.1, pp.85-96, 2012.   DOI
3 Q. Xu, T. M. Chen, Y. Hu, and P. Gong, "Write pattern format algorithm for reliable NAND-Based SSDs," IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.61, No.7, pp.516-520, 2014.   DOI
4 W. Zhang, Q. Cao, and Z. Lu, "Bit-Flipping schemes upon MLC flash: Investigation, implementation, and evaluation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.38, No.4, pp.780-784, 2019.   DOI
5 P. Cappelletti, R. Bez, D. Cantarelli, and L. Fratin, "Failure mechanisms of flash cell in program/erase cycling," in Proceedings of 1994 IEEE International Electron Devices Meeting, pp.291-294, 1994.
6 C. Lee, et al., "A 32-Gb MLC NAND flash memory with vth endurance enhancing schemes in 32 nm CMOS," IEEE Journal of Solid-State Circuits, Vol.46, No.1, pp.97-106, 2011.   DOI
7 D. Wei, L. Deng, P. Zhang, L. Qiao, and X. Peng, "NRC: A nibble remapping coding strategy for NAND flash reliability extension," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.35, No.11, pp.1942-1946, 2016.   DOI
8 J. Guo, Z. Chen, D. Wang, Z. Shao, and Y. Chen, "DPA: A data pattern aware error prevention technique for NAND flash lifetime extension," in 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 592-597, 2014.
9 W. Lee, M. Kang, S. Hong, and S. Kim, "Interpage-based endurance-enhancing lower state encoding for MLC and TLC flash memory storages," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.27, No.9, pp.2033-2045, 2019.   DOI
10 C. Kim, et al., "A 21nm high performance 64Gb MLC NAND flash memory with 400MB/s asynchronous toggle DDR interface," in 2011 Symposium on VLSI Circuits - Digest of Technical Papers, pp.196-197, 2011.
11 J. Cha and S. Kang, "Data randomization scheme for endurance enhancement and interference mitigation of multilevel flash memory devices," ETRI Journal, Vol.35, pp.166-169, 2013.   DOI
12 N. Mielke, et al., "Bit error rate in NAND flash memories," IEEE International Reliability Physics Symposium, pp.9-17, 2008.
13 K. Lee, M. Kang, S. Seo, D. H. Li, J. Kim, and H. Shin, "Analysis of failure mechanisms and extraction of Activation Energies (Ea) in 21-nm nand flash cells," IEEE Electron Device Letters, Vol.34, No.1, pp.48-50, 2013.   DOI
14 K. Lee, D. Kang, H. Shin, S. Kwon, S. Kim, and Y. Hwang, "Analysis of failure mechanisms in erased state of sub 20-nm nand flash memory," in 2014 44th European Solid State Device Research Conference (ESSDERC), pp.58-61, 2014.
15 Y. Cai, S. Ghose, Y. Luo, K. Mai, O. Mutlu, and E. F. Haratsch, "Characterizing, exploiting, and mitigating vulnerabilities in MLC NAND flash memory programming," 2018.
16 Y. Cai, S. Ghose, Y. Luo, K. Mai, O. Mutlu, and E. F. Haratsch, "Vulnerabilities in MLC NAND flash memory programming: Experimental analysis, exploits, and mitigation techniques," in 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 49-60, 2017.