Browse > Article
http://dx.doi.org/10.3745/KIPSTA.2012.19A.3.113

Simulation Method based on Design Checkpoint for Efficient Debugging  

Shim, Kyu-Ho (삼성전자 System LSI 사업부)
Kim, Nam-Do (삼성전자 System LSI 사업부)
Park, In-Hag ((주)시스템센트로이드)
Min, Byeong-Eon (삼성전자 System LSI 사업부)
Yang, Sei-Yang (부산대학교 컴퓨터공학과)
Publication Information
The KIPS Transactions:PartA / v.19A, no.3, 2012 , pp. 113-120 More about this Journal
Abstract
The visibility for signals in designs is required for their analysis and debug during the verification process. It could be achieved through the signal dumping for designs during the execution of HDL simulation. However, such signal dumping, in general, degrades the speed of simulation significantly, or can result in the number of simulation runs. In this paper, we have proposed an efficient and fast simulation method for dumping based on the design checkpoint, and shown its effectiveness by applying it to industrial SOC designs.
Keywords
Verification; Simulation; Debugging;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Yu-Chin Hsu, "Maximizing Full-Chip Simulation Signal Visibility for Efficient Debug", International Symposium on VLSI Design, Automation and Test, pp.1-5, 2007.
2 Visibility Enhancement Technology for Simulation Whitepaper, Novas Software (http://www.springsoft.com), 2009
3 Dusung Kim, Maciej Ciesielski, Kyuho Shim, and Seiyang Yang, "Temporal parallel simulation: A fast gate-level HDL simulation using higher level models", Proc. DATE Conference, March, pp.1584-1589, 2011.
4 Making Hardware/Software Co-Verification Easier for ARM $Cortex^{TM}$ - A Series Processor-based Designs, On-Demand Web Seminar, Mentor Graphics (http://www.mentor.com), 2012.
5 P. Rashinkar, P. Paterson, and L. Singh, System-on-a-chip Verification: Methodology and Technique, Kluwer Academic Publishers, Dec., 2000.
6 J. Marantz, "Enhanced Visibility and Performance in Functional Verification by Reconstruction" Proc. 35th Design Automation Conference, pp.164-169, June, 1998.
7 B. Wile, J. Goss, and W. Roesner, Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon) , Elsevier, June, 2005.
8 Kyuho Shim, Youngrae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej Ciesielski, and Seiyang Yang, "A Fast Two-pass HDL Simulation with On-Demand Dump", Asia and South Pacific Design Automation Conference, 2008. pp.422-427, 2008.
9 Namdo Kim, Junhyuk Park, Byeong Min, K.M. Choi, Kyuho Shim and Seiyang Yang, "Smart Debugging Strategy for Billion-Gate SOCs", User Track, 47th Design Automation Conference, June, 2010.