Browse > Article
http://dx.doi.org/10.3745/KIPSTA.2008.15-A.4.217

Branch Prediction with Speculative History and Its Effective Recovery Method  

Kwak, Jong-Wook (영남대학교 전자정보공학부)
Abstract
Branch prediction accuracy is critical for system performance in modern microprocessor architectures. The use of speculative update branch history provides substantial accuracy improvement in branch prediction. However, speculative update branch history is the information about uncommitted branch instruction and thus it may hurts program correctness, in case of miss-speculative execution. Therefore, speculative update branch history requires suitable recovery mechanisms to provide program correctness as well as performance improvement. In this paper, we propose recovery logics for speculative update branch history. The proposed solutions are recovery logics for both global history and local history. In simulation results, our solution provides performance improvement up to 5.64%. In addition, it guarantees the program correctness and almost 90% of additional hardware overhead is reduced, compared to previous works.
Keywords
Branch Prediction; Global/Local Branch History; Speculative History; Recovery Logic;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Yeh, T. Y. and Patt, Y. N., “Two-level adaptive branch prediction,” In Proceedings of the 24th ACM/IEEE International Symposium on Microarchitecture, 51-61, 1991
2 K. Skadron, M. Martonosi, and D. Clark. “Speculative updates of local and global branch history: A quantitative analysis,” JILP, Vol.2, Jan., 2000
3 S. Jourdan, J. Stark, T.-H. Hsing, and Y. N. Patt, “Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution,” International Journal of Parallel Programming, Vol.25, pp.363-383, Oct., 1997   DOI
4 S. Sechrest, S., C.-C.Lee, T. Mudge, “Correlation and Aliasing in Dynamic Branch Predictors,” in Proceedings of the 23rd ISCA, 22-32, 1996
5 D. Burger, T. M. Austin, and S. Bennett, “Evaluating future micro-processors: the SimpleScalar tool set,” Tech. Report TR-1308, Univ. of Wisconsin-Madison Computer Sciences Dept., 1997
6 SPEC CPU2000 Benchmarks, http://www.specbench.org
7 A. R. Talcott, W. Yamamoto, M. J. Serrano, R. C.Wood, and M. Nemirovsky, “The impact of unresolved branches on branch prediction scheme performance,” in Proceedings of the 21st Annual International Symposium on Computer Architecture, pp.12-21, Apr., 1994
8 A. Seznec, S. Felix, V. Krishnan, and Y. Sazeid'es. “Design tradeoffs for the ev8 branch predictor,” In Proc. of the 29th ISCA, pp.295-306, May, 2002
9 M. Evers, S. J. Patel, R. S. Chapell, and Y. N. Patt, “An analysis of correlation and predictability: What makes two-level branch predictors work,” In Proceedings of the 25th Annual Intl. Symposium on Computer Architecture, pages 52-61, June, 1998
10 A. R. Talcott, M. Nemirovsky, and R. C. Wood, “The Influence of Branch Prediction Table Interference on Branch Prediction Scheme Performance,” International Conference on Parallel Architectures and Compilation Techniques, 1995
11 Chih-Chieh Lee, I. K. Chen, and T. Mudge, “The Bi-Mode Branch Predictor,” International Symposium on Microarchitecture, 1997
12 Eric Sprangle, R. Chappell, M. Alsup, and Y. Patt, “The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference,” Intl. Symposium on Computer Architecture, 1997
13 S. Kim and G. Tyson, “Analyzing the working set characteristics of branch execution,” in Proceedings of the 31st Annual ACM/IEEE International Symposium on Microarchitecture, pp.49-58, Dec., 1998
14 R. E. Kessler, “The Alpha 21264 Microprocessor,” IEEE Micro, Volume 19, Issue 2, pp.24-36, 1999   DOI   ScienceOn
15 E. Sprangle and D. Carmean, “Increasing processor performance by implementing deeper pipelines,” In Proc. 29th Int'l Symp. on Computer Architecture, pp.25-34, 2002
16 R. Tomasulo, “An efficient algorithm for exploiting multiple arithmetic units,” IBM J. Research and Development 11:1(January), 25-33, 1967   DOI
17 A. R. Talcott,W. Yamamoto,M. J. Serrano, R. C.Wood, and M. Nemirovsky, “The impact of unresolved branches on branch prediction scheme performance,” in Proceedings of the 21st ISCA, pp.12-21, Apr., 1994
18 E. Hao, P.-Y. Chang, and Y. Patt, “The effect of speculatively updating branch history on branch prediction accuracy, revisited,” in Proceedings of the 27th Annual International Symposium onMicroarchitecture, pp.228-232, Nov., 1994
19 T.-Y. Yeh and Y. N. Patt, “Alternative implementations of two-level adaptive branch prediction,” In Proc. of the 19th ISCA, pp.124-134, May, 1992
20 E. Hao, P.-Y. Chang, and Y. Patt, “The effect of speculatively updating branch history on branch prediction accuracy, revisited,” in Proceedings of the 27th MICRO, pp.228-232, Nov., 1994
21 E. J. McLellan, D. A. Webb, “The Alpha 21264 Microprocessor Architecture,” In Proceedings of the International Conference on Computer Design, pp.90-95, IEEE, 1998
22 McFarling, S., “Combining branch predictors,” Tech. Rep. TN-36m, Digital Western Research Lab., June, 1993