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http://dx.doi.org/10.3745/KIPSTC.2005.12C.1.011

A Gigabit Rate Packet Header Collector using Network Processor  

Choi Pan-an (아주대학교 정보통신전문대학원)
Choi Kyung-hee (아주대학교 정보통신전문대학원)
Jung Gi-hyun (아주대학교 전자공학부)
Sim Jae-hong (조선대학교 인터넷소프트웨어공학부)
Publication Information
The KIPS Transactions:PartC / v.12C, no.1, 2005 , pp. 11-18 More about this Journal
Abstract
This paper proposes a packet header collector, based on a network processor with multi-processor and multi-threads, that shows a high throughput on gigabit network. The proposed collector has an architecture to separate packets coming from gigabit network into headers and payloads, and distribute them to multiple 100Mbit MAC ports. The architecture hiring a unique buffer management method and load distribution strategy among multiple processors is evaluated empirically in depth.
Keywords
network Processor; packet header collector; load distribution;
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