1 |
Power estimation tutorial with Synopsys tools, http://www.tkt.cs.tut.fi/tools/public/tutorials/synopsys/ pwr_est/gspe.html#rtl_pwr_est_flow
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2 |
Synopsys, "Power Compiler User Guide", https://solvnet.synopsys.com/dow_retrieve/E-2010.09/ ni/power.html#Power%20Compiler
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3 |
K.Kobayashi, J.Ikegami, S. Matsuo, Evaluation of Hardware Performance for the SHA-3 Candidates Using SASEBO-GII, http://www.iacr.org
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4 |
http://www.synopsys.com, Power Compiler Reference Manual
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5 |
Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski: Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs. CHES 2010: 264-278
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6 |
D. Soundris, C.Piquet, C Goutis, Designing CMOS Circuits for Low Power, Springer Verlag, 2010.
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7 |
Cryptographic Hash Project, available at http://csrc.nist.gov/groups/ST/hash/index.html
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