1 |
X. Ruan and R. Katti, "An Efficient Data-Independent Technique for Compressing Test Vectors in Systems-on-a-Chip," Proc. IEEE Emerging VLSI Tech. Arch. Symp., 2006, p. 153.
|
2 |
A.H. El-Maleh and R.H. Al-Abaji, "Extended Frequency- Directed Run Length Code with Improved Application to System-on-a-Chip Test Data Compression," Proc. 9th IEEE Int. Conf. Electron., Circuits Syst., 2002, p. 449.
|
3 |
A.H. El-Maleh, "Efficient Test Compression Technique Based on Block Merging," IET Comput. Digit. Tech., vol. 2, no. 5, 2008, pp. 327-335.
DOI
ScienceOn
|
4 |
L.-J. Lee et al., "A Multi-Dimensional Pattern Run-Length Method for Test Data Compression," Proc. Asian Test Symp., 2009, pp. 111-116.
|
5 |
I. Hamzaoglu and J.H. Patel, "Test Set Compaction Algorithms for Combinational Circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 8, 2000, pp. 957-963.
DOI
ScienceOn
|
6 |
X. Kavousianos, E. Kalligeros, and D. Nikolos, "Optimal Selective Huffman Coding for Test-Data Compression," IEEE Trans. Comput., vol. 56, no. 8, 2007, pp. 1146-1152.
DOI
|
7 |
A. Chandra and K. Chakrabarty, "Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes," IEEE Trans. Comput., vol. 52, no. 8, 2003, pp. 1076-1088.
DOI
ScienceOn
|
8 |
P.T. Gonciari, B. Al-Hashimi, and N. Nicolici, "Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression," Proc. Design Autom. Test Europe, Paris, 2002, p. 604.
|
9 |
M. Tehranipoor, M. Nourani, and K. Chakrabarty, "Nine-Coded Compression Technique for Testing Embedded Cores in SoCs," IEEE Trans. VLSI Syst., vol. 13, no. 6, 2005, pp. 719-731.
DOI
|
10 |
A. Chandra and K. Chakrabarty, "System-on-a-Chip Data Compression and Decompression Architecture Based on Golomb Codes," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 3, 2001, pp. 355-368.
DOI
ScienceOn
|
11 |
A. Chandra and K. Chakrabarty, "A Unified Approach to Reduce SoC Test Data Volume, Scan Power and Testing Time," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 3, 2003, pp. 352-363.
DOI
ScienceOn
|
12 |
S. Mitra and K.S. Kim, "X-Compact: An Efficient Response Compaction Technique," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, 2004, pp. 421-432.
DOI
ScienceOn
|
13 |
J. Rajski et al., "Embedded Deterministic Test," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, 2004, pp. 776-792.
DOI
ScienceOn
|
14 |
D.A. Huffman, "A Method for the Construction of Minimum Redundancy Codes," Proc. IRE, 1952, p. 1098.
|
15 |
S. Mitra and K.S. Kim, "XMAX: X-Tolerant Architecture for Maximal Test Compression," Proc. IEEE Int. Conf. Comput. Design, 2003, p. 326.
|
16 |
B. Koenemann et al., "A SmartBIST Variant with Guaranteed Encoding," Proc. Asia Test Symp., 2001, p. 325.
|
17 |
N.A. Touba, "Survey of Test Vector Compression Techniques," IEEE Design Test Comput., vol. 23, no. 4, 2006, pp. 294-303.
DOI
|
18 |
A. Jas et al., "An Efficient Test Vector Compression Scheme Using Selective Huffman Coding," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 6, 2003, pp. 797-806.
DOI
ScienceOn
|