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A VSSI-CRL Synthetic Control Chart  

Lee Jae-Won (숭실대학교 산업 정보시스템공학과)
Lim Tae-Jin (숭실대학교 산업 정보시스템공학과)
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Abstract
We propose a VSSI-CRL(Variable Sampling Size and Samplina Interval-Conforming Run length) synthetic control chart in order to improve the statistical characteristics of both the VSSI chart and the CRL synthetic chart. The VSSI-CRL chart utilizes VSSI sampling scheme, but it produces a signal only when the CRI is less than a given limit. An algorithm for calculating the ARL(Average Run length) and ATS(Average Time to Signal) of the VSSI-CRL chart is developed by employing Markov chain method. We present some lemmas for describing the statistical characteristics of the VSSI-CRL chart under in-control state. A procedure for designing the VSSI-CRL chart is proposed based on the lemmas. Extensive comparative studios show that the VSSI-CRL chart is superior to the CRL synthetic chart or the VSSI chart in general, and is comparable to the EWMA chart in ATS performance.
Keywords
VSSI Chart; CRL Chart; ARL; ATS; Statistical Design; Markov Chain;
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