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An Optimal Instruction Fetch Strategy for SMT Processors  

홍인표 (연세대학교 전기전자공학과 프로세서연구실)
문병인 (연세대학교 전기전자공학과 프로세서연구실)
김문경 (연세대학교 전기전자공학과 프로세서연구실)
이용석 (연세대학교 전기전자공학과 프로세서연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.27, no.5C, 2002 , pp. 512-521 More about this Journal
Abstract
Recently, conventional superscalar RISC processors arrive their performance limit, and many researches on the next-generation architecture are concentrated on SMT(Simultaneous Multi-Threading). In SMT processors, multiple threads are executed simultaneously and share hardware resources dynamically. In this case, it is more important to supply instructions from multiple threads to processor core efficiently than ever. Because SMT architecture shows higher IPC(Instructions per cycle) than superscalar architecture, performance is influenced by fetch bandwidth and the size of fetch queue. Moreover, to use TLP(Thread Level Parallelism) efficiently, fetch thread selection algorithm and fetch bandwidth for each selected threads must be carefully designed. Thus, in this paper, the performance values influenced by these factors are analyzed. Based on the results, an optimal instruction fetch strategy for SMT processors is proposed.
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  • Reference
1 ARM, ARM Architecture Reference Manual, Part A CPU Architecture, 1996
2 Clearwater Networks, Inc. 'Introducing the CNP810 Farnily of Network Services Processors', http://www.clearwaternetworks.con/c1earwater_overview.pdf, June 2001
3 ARM, ARM Developer Suit version 1.1, Compiler, Linker and Utilities Guide, 1999
4 Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm, Dean M. Tullsen, 'SIMULTANEOUS MULTITHREADING: A Platform for Next-Generation Processors', September/October 1997 IEEE Micro, p.p. 12-19
5 H. Hirata, K. Kimura, S. Nagamme, Y. Mochizuki, A. Nishimura, Y. Nakase, and T. Nishizawa, 'An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads,' Proc. 19th Annual International Symposium on Computer Architecture, pp. 136-145, May 1992
6 Mike Johnson, Superscalar Microprocessor Design, pp. 107-108, Prentice-Hall, Inc. 1991
7 D.M. Tullsen, S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, and R.L. Stannn, 'Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor,' Proc. 23rd Annual International Symposium on Computer Architecture, pp. 191-202, May 1996