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A VLSI Architecture for the Binary Jacket Sequence  

박주용 (서남대학교 전기전자멀티미디어공학부)
이문호 (서남대학교 전기전자멀티미디어공학부)
Abstract
The jacket matrix is based on the Walsh-Hadamard matrix and an extension of it. While elements of the Walsh-Hadamard matrix are +1, or -1, those of the Jacket matrix are ${\pm}$1 and ${\pm}$$\omega$, which is $\omega$, which is ${\pm}$j and ${\pm}$2$\sub$n/. This matrix has weights in the center part of the matrix and its size is 1/4 of Hadamard matrix, and it has also two parts, sigh and weight. In this paper, instead of the conventional Jacket matrix where the weight is imposed by force, a simple Jacket sequence generation method is proposed. The Jacket sequence is generated by AND and Exclusive-OR operations between the binary indices bits of row and those of column. The weight is imposed on the element by when the product of each Exclusive-OR operations of significant upper two binary index bits of a row and column is 1. Each part of the Jacket matrix can be represented by jacket sequence using row and column binary index bits. Using Distributed Arithmetic (DA), we present a VLSI architecture of the Fast Jacket transform is presented. The Jacket matrix is able to be applied to cryptography, the information theory and complex spreading jacket QPSK modulation for WCDMA.
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