| 1 | Cisco CRS-1 Overview, available at www.cs.ucsd.edu/~varghese/crs1.ppt |
| 2 | W. Kwon, et al., 'A Practical Approach of Memory Access Parallelization to Exploit Multiple Off-chip DDR Memories' , Proc, Design Automation Conference, June 2008 |
| 3 | J. Held, J. Bautista, and S. Koehl, 'From a Few Cores to Many' , Intel white paper available at ftp://download.intel.com/research/platform/terascale/t erascale_overview_paper.pdf |
| 4 | L. Seiler, et al., 'Larrabee: A Many-Core x86 Architecture for Visual Computing' , ACM Transactions on Graphics, August 2008 |
| 5 | nVidia Tesla S1070, http://www.nvidia.com/object/tesla_s1070.html |
| 6 | Microsoft, SXM: C# Software Transactional Memory, 2005 |
| 7 | Microsoft Co., 'The Manycore Shift: Microsoft Parallel Computing Initiative Ushers Computing into Next Era' , Microsoft white paper available at www.microsoftcom/presspass/events/supercomputing /docs/ManycoreWP.doc, Nov. 2007 |
| 8 | C. Kim, D. Burger, and S, Keckler, 'An adaptive, nonuniform cache structure for wire-delay dominated on-chip caches' , Proc, International Conference on Architectural Support for Programming Languages and Operating Systems, 2003 |
| 9 | S. Borkar, 'Thousand Core Chips - A Technology Perspective' , Proc. Design Automation Conference, June 2007 |
| 10 | Weirong Zhu, et al. 'Exploring Financial Applications on Many-Core-on-a-Chip Architecture: A First Experiment'. Proc, ISPA Workshops 2006 |
| 11 | A. Kumar, et al., 'Express virtual channels: towards the ideal interconnection fabric' , Proc. International Symposium on Computer Architecture, 2007 |
| 12 | T. Krishna, et al, 'NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication' , Symposium on High Performance Interconnects, Aug. 2008 |
| 13 | P, Dubey, 'Recognition, Mining and Synthesis Moves Computers to the Era of Tera.' Intel Technology Journal, Feb. 2005 |
| 14 | B. Beckmann and D. Wood, 'TLC: Transmission Line Caches' , Proc, IEEE/ACM International Symposium on Microarchitecture, 2003 |
| 15 | C. Garcia, et al. 'Mitosis Compiler:An Infrastructure for Speculative Threading Based on Pre-Computation Slices' , Proc. Conference on Programming Language Design and Implementation, 2005 |
| 16 | S. Vangal, et al., 'An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS' , IEEE Journal of Solid State Circuits.Jan, 2008 |
 |
Korea Institute of Science and Technology Information
Gwahangno, Yuseong-gu, Daejeon, 305-806, Korea TEL : +82-42-869-1752
Copyright (c) 2009 KISTI. All Rights Reserved. For more information mail to
webmaster
