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http://dx.doi.org/10.5573/IEIESPC.2015.4.1.051

Digital Error Correction for a 10-Bit Straightforward SAR ADC  

Rikan, Behnam Samadpoor (College of Information and Communication Engineering, Sungkyunkwan University)
Abbasizadeh, Hamed (College of Information and Communication Engineering, Sungkyunkwan University)
Do, Sung-Han (College of Information and Communication Engineering, Sungkyunkwan University)
Lee, Dong-Soo (College of Information and Communication Engineering, Sungkyunkwan University)
Lee, Kang-Yoon (College of Information and Communication Engineering, Sungkyunkwan University)
Publication Information
IEIE Transactions on Smart Processing and Computing / v.4, no.1, 2015 , pp. 51-58 More about this Journal
Abstract
This paper proposes a 10-b SAR ADC. To increase the conversion speed and reduce the power consumption and area, redundant cycles were implemented digitally in a capacitor DAC. The capacitor DAC algorithm was straightforward switching, which included digital error correction steps. A prototype ADC was implemented in CMOS $0.18-{\mu}m$ technology. This structure consumed $140{\mu}W$ and achieved 59.4-dB SNDR at 1.25MS/s under a 1.8-V supply. The figure of merit (FOM) was 140fJ/conversion-step.
Keywords
Redundancy; Digital error correction; Straightforward; SAR ADC;
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1 W. Liuet, P. Huang and Y. Chiu, "A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter with Digital Calibration," IEEE Journal of Solid-State Circuits, VOL. 46, NO. 11, Nov. 2011.
2 S-H. Cho, C-K. Lee, J-K. Kwon and S-T. Ryu, "A 550-uW 10-b 40-MS/s SAR ADC with Multistep Addition-Only Digital Error Correction," IEEE Journal of Solid-State Circuits, VOL. 46, NO. 8, Aug. 2011.
3 B. Kim, L. Yan, J. Yoo, N. Cho and H-J Yoo, "An Energy-Efficient Dual Sampling SAR ADC with Reduced Capacitive DAC," Circuits and Systems, ISCAS. IEEE International Symposium, 2009.
4 V. Hariprasath, J. Guerber, S-H. Lee and U-K. Moon, "Merged capacitor switching based SAR ADC with highest switching energy-efficiency," Electronic Letters, 2010.
5 Y. Chen, S. Tsukamoto and T. Kuroda, "A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS," IEEE Asian Solid-State Circuits Conference pp. 16-18, Nov. 2009.
6 Y. Zhu, C-H. Chan, U-F. Chio, S-W. Sin, S-Pan U, R. P. Martins and F. Maloberti, "A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS," IEEE Journal of Solid-State Circuits, VOL. 45, NO. 6, Jun. 2010.
7 P. W. LI, M. J. Chin, P. R. Gray and R. Castello, "A Ratio-Independent Algorithmic Analog-to-Digital Conversion Technique," IEEE Journal of Solid-State Circuits, VOL. SC-19, NO.6, Dec. 1984.
8 S-H. Cho, C-K. Lee, J-K. Kwon, and S-T. Ryu, "A $550\mu{W}$ 10b 40MS/s SAR ADC with Multistep Addition-only Digital Error Correction," Custom Integrated Circuits Conference (CICC), 2010.
9 C. Jun, R. Feng and Xu M. H., "IC Design of 2Ms/s 10-bit SAR ADC with Low Power," High Density Packaging and Microsystem Integration, 2007.
10 H-K. Kim, Y-J. Min, Y-H. Kim and S-W. Kim, "A Low Power Consumption 10-bit Rail-to-Rail SAR ADC Using a C-2C Capacitor Array," Electron Devices and Solid-State Circuits (EDSSC), IEEE International Conference on, 2008.