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http://dx.doi.org/10.5626/JCSE.2014.8.1.25

Comparing Separate and Statically-Partitioned Caches for Time-Predictable Multicore Processors  

Wu, Lan (Department of Electrical and Computer Engineering, Virginia Commonwealth University)
Ding, Yiqiang (Department of Electrical and Computer Engineering, Virginia Commonwealth University)
Zhang, Wei (Department of Electrical and Computer Engineering, Virginia Commonwealth University)
Publication Information
Journal of Computing Science and Engineering / v.8, no.1, 2014 , pp. 25-33 More about this Journal
Abstract
In this paper, we quantitatively compare two different time-predictable multicore cache architectures, separate and statically-partitioned caches, through extensive simulation. Current research trends primarily focus on partitioned-cache architectures in order to achieve time predictability for hard real-time multicore based systems, and our experiments reveal that separate caches actually lead to much better performance and energy efficiency when compared to statically-partitioned caches, and both of them are adequate for timing analysis for real-time multicore applications.
Keywords
Performance; Reliability; Hard real-time systems; Multicore processors; Cache architectures; WCET analysis;
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1 SimpleScalar, http://www.simplescalar.com/.
2 S. A. Edwards and E. A. Lee, "The case for the precision timed (PRET) machine," in Proceedings of the 44th ACM/IEEE Design Automation Conference, San Diego, CA, 2007, pp. 264-265.
3 A. Hansson, K. Goossens, M. Bekooij, and J. Huisken, "CoMPSoC: a template for composable and predictable multi-processor system on chips," ACM Transactions on Design Automation of Electronic Systems, vol. 14, no. 1, article no. 2, 2009.
4 D. Hardy and I. Puaut, "WCET analysis of multi-level noninclusive set-associative instruction caches," in Proceedings of the 29th Real-Time Systems Symposium, Barcelona, Spain, 2008, pp. 456-466.
5 CACTI, http://www.hpl.hp.com/research/cacti/.
6 SPEC CPU2006, http://www.spec.org/cpu2006/.
7 W. Zhang and J. Yan, "Accurately estimating worst-case execution time for multi-core processors with shared directmapped instruction caches," in Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, Beijing, China, 2009, pp. 455-463.
8 J. Reineke, D. Grund, C. Berg, and R. Wilhelm, "Timing predictability of cache replacement policies," Real-Time Systems, vol. 37, no. 2, pp. 99-122, 2007.   DOI
9 J. Stohr, A. von Bulow, and G. Farber, "Bounding worst-case access times in modern multiprocessor systems," in Proceedings of the 17th Euromicro Conference on Real-Time Systems, Palma de Mallorca, Spain, 2005, pp. 189-198.
10 R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, and P. Stenstrom, "The worst-case execution-time problem: overview of methods and survey of tools," ACM Transactions on Embedded Computing Systems, vol. 7, no. 3, article no. 36, 2008.
11 J. M. Calandrino, J. H. Anderson, and D. P. Baumberger, "A hybrid real-time scheduling approach for large-scale multicore platforms," in Proceedings of the 19th Euromicro Conference on Real-Time Systems, Pisa, Italy, 2007, pp. 247-258.
12 Y. Li, V. Suhendra, Y. Liang, T. Mitra, and A. Roychoudhury, "Timing analysis of concurrent programs running on shared cache multi-cores," in Proceedings of the 30th IEEE Real-Time System Symposium, Washington, DC, 2009, pp. 57-67.
13 C. A. Healy, D. B. Whalley, and M. G. Harmon, "Integrating the timing analysis of pipelining and instruction caching," in Proceedings of the 16th Real-Time Systems Symposium, Pisa, Italy, 1995, pp. 288-297.
14 J. Rosen, A. Andrei, P. Eles, and Z. Peng, "Bus access optimization for predictable implementation of real-time application on multiprocessor system-on-chip," in Proceedings of the 28th IEEE International Real-Time Systems Symposium, Tucson, AZ, 2007, pp. 49-60.
15 J. Yan and W. Zhang, "WCET analysis for multi-core processors with shared L2 instruction caches," in Proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium, St. Louis, MO, 2008, pp. 80-89.
16 S. Chattopadhyay, C. L. Kee, A. Roychoudhury, T. Kelter, P. Marwedel, and H. Falk, "A unified WCET analysis framework for multi-core platforms," in Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, Beijing, China, 2012, p. 99-108.
17 T. Kelter, H. Falk, P. Marwedel, S. Chattopadhyay, and A. Roychoudhury, "Bus-aware multicore WCET analysis through TDMA offset bounds," in Proceedings of the 23rd Euromicro Conference on Real-Time Systems, Porto, Portugal, 2011, pp. 3-12.
18 L. Wu and W. Zhang, "A model checking based approach to bounding worst-case execution time for multicore processors," ACM Transactions on Embedded Computer Systems, vol. 11, no. S2, article no. 56, 2012.
19 Malardalen WCET benchmarks, http://www.mrtc.mdh.se/projects/wcet/benchmarks.html.
20 M. Paolieri, E. Quinones, F. J. Cazorla, G. Bernat, and M. Valero, "Hardware support for WCET analysis of hard realtime multicore systems," in Proceedings of the 36th Annual International Symposium on Computer Architecture, Austin, TX, 2009, pp. 57-68.