Optimizing Mutiple Quality Characteristics of Through Silicon Via(TSV) Interface and Solder Joint Interface by Numerical Analysis-based Taguchi Method |
Bang, Han-Sur
(조선대학교 선박해양공학과)
Bang, Hee-Seon (조선대학교 선박해양공학과) Park, Se-Min (조선대학교 선박해양공학과) Lee, Chang-Woo (한국생산기술연구원 수석연구원) |
1 | W. Engelmaier, Fatigue life of lead less chip carrier solder joints during power cycling, in: IEEE Trans actions on Component, Hybrids, and Manufacturing Technology, vol. CHMT-6, No.3, September 1983. DOI |
2 | Y.E.Shin, Y.S.Kim, J.M.Kim and M.G.Choi : The thermal Fatigue Analysis and Life Evaluation of Solder Joint for Flip Package using Darveaux Mothod, Journal of KWS, 22-6 (2004), 522-528 (in Korean) |
3 | S.Yo. Wook, D. Witarsa, S.Y.M. Lim, V. Ganesh, A.G.K. Viswanath, T.C. Chai, K.O. Navas, V. Kripesh, Reliab ility studies of a through silicon via stacked module for 3D micro system packaging, in: Electronic Components and Technology Conference, 2006, 1449-1453 |
4 | K. Darbha, J.H. Okura, S. Shetty, A. Dasgupta, T. Reinikainen, J. Zhu, J.F.J.M. Caers, Transaction of ASMEJournal of Electronic Packaging 121 (1999) 238-241 |
5 | P.S. Andry, C. Tsang, E. Sprogie, C. Patel, S.L. Wright, B.C. Webb, L.P. Buchwalter, D. Manzer, R. Horton, R. Polastre, J. ickerbocker, OS-compa tible process for fabricating electrical through silicon vias, RC23867 (W0 602-049) February 3rd, 2006, Electrical gineering |
6 | B. Shekhar, 3D Technology a System Perspective, Intel Corp. Nov. 8, 2008 |
7 | J. Zhang, M.O. Bloomfield, J.Q. Lu, R.J. Gutmann, T.S. Cale, Microelectr onic Engineering 82 (2005) 534-547 DOI ScienceOn |
8 | S.J.Hong, K.S.Kim, Norman Zhou and J.P.Jung : 3 Dimension Packaging Technology Using Via, Journal of KWS, 24-2 (2006), 137-141 (in Korean) |
9 | Leila J. Ladani, Numerical analysis of thermomechanical reliability of thr ough silicon vias (TSVs) and solder interconnects in 3-dimensional integ rated circuits, Microelectronic Engineering 87 (2010) 208-215 DOI ScienceOn |
10 | Tsai Ming-Yi, Jeter CH, Otto Wang T., Investigation of thermo-mechanical behaviors of flip-chip BGA pac kages during manufacturing process and thermal cycling, IEEE Trans Compon Pack Technol 2004. 27 (3) |
11 | E. Beyne, B. Swinnen, 3D system integration, in: IEEE, International Conference on IC Design and Technology, ICICDT, 2007 |
12 | Seunghyun Cho, Soonjin Cho, Jose ph Y. Lee, Estimation of warpage and thermal stress of IVHs in flip-chip ball grid arrays package by FEM, Microelectronics Reliability 48 (2008) 300-309 DOI ScienceOn |
13 | G. Taguchi, Taguchi Methods: Design of Experiment, Book, Quality Engineering Series, American Supplier Institute, 1993 |