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Efficient Cache Architecture for Transactional Memory  

Choi, Dong-Min (Department of Electrical and Electronic Engineering, Yonsei University)
Kim, Seung-Hun (Department of Electrical and Electronic Engineering, Yonsei University)
Ro, Won-Woo (Department of Electrical and Electronic Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea CI / v.48, no.4, 2011 , pp. 1-8 More about this Journal
Abstract
Traditional transactional memory systems are no longer able to guarantee the performance of diverse applications with overflowed transactions since there is the drawback that tracking the data for logging is difficult. Especially, this mechanism has a disadvantage of increasing communication delay for sustaining the state which is required to detect the conflict on the overflowed transactions from the first level cache in the transactional memory systems. To address this point, we have focused on the cache architecture of the systems to reduce the overhead caused by overflows and cache misses. In this paper, we present Supportive Cache which reduces additional overhead during transactions. Supportive Cache performs a parallel look-up with L1 private cache and uses the same replacement policy as L1 private cache. We evaluate the performance of the proposed design by comparing LogTM-SE with and without Supportive Cache. The simulation results show that our system improves the performance by 37% on average, compared to the original LogTM-SE which uses the same hardware resource.
Keywords
Transactional Memory; Parallel processing; Victim Cache; Supportive Cache;
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Times Cited By KSCI : 1  (Citation Analysis)
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