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Research on Event Mechanism for Reducing Power Overheads in Cache Memory Synchronization  

Pak, Young-Jin (School of Electrical & Electronic Engineering, Yonsei University)
Jeong, Ha-Young (School of Electrical & Electronic Engineering, Yonsei University)
Lee, Yong-Surk (School of Electrical & Electronic Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea CI / v.48, no.3, 2011 , pp. 69-75 More about this Journal
Abstract
In this paper, we propose an anycast event driven synchronization mechanism to reduce power overheads. Our proposed mechanism can reduce unnecessary polling operations on SHI(Snoop Hit Invalidate) or SHR(Snoop Hit Read) states. It prevents waisting bandwidth and reduces power overheads on polling operation. Also it decreases transition power of state change compared to broadcast model. Simulation results indicated that the proposed architecture had about 15.3% of power decrease compared to spin-lock model and about 4.7% of power decrease compared to broadcast model. Overall results indicated that proposed synchronization mechanism could increase power efficiency of multi-core system by reducing power overheads.
Keywords
멀티스레드 프로세서;공유 메모리 구조;이벤트 드리븐 메커니즘;프로세스 동기화;
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  • Reference
1 John Goodacre, "Low Power Processing: Use Only the Power Needed to Get the Job Done," on ARM Technical Report, Dec. 2008.
2 Binkert N.L., Dreslinski R.G., Hsu L.R., Lim, K.T., Saidi A.G., Reinhardt S.K., "The M5 Simulator: Modeling Networked Systems," on Micro, Vol. 26, no. 4, pp.52-60, Aug. 2006.
3 S. Woo, M. Ohara, E. Torrie, J.P. Singh, A. Gupta. "The SPLASH-2 programs: Characterization and methodological considerations," in Proc. of the 22th International Symposium on Computer Architecture, Vol. 23 no. 2, Italy, June 1995.
4 리처드 로(Richard Low), "마이크로 프로세서 동향과 멀티 코어, 메모리 및 전원 관리," Freescale Semiconductor Report, 2007.
5 Luca Benini, Alessandro Bogliolo, and Giovanni De Micheli "A Survey of Design Techniques for System-Level Dynamic Power Management," IEEE Trans. on Very Large Scale Integration Systems, Vol. 8, no. 3, pp.299-316, JUNE 2000.   DOI
6 Monchiero. M, Palermo. G, Silvano. C, Villa. O, "Efficient Synchronization for Embedded On-Chip Multiprocessors," IEEE Trans. on Very Large Scale Integration Systems, Vol. 14, no. 10, pp.1049-1062, Oct. 2006.   DOI
7 Shaoshan. Liu, Jean-Luc Gaudiot, "Synchronization Mechanisms on Modern Multi-core Architecture," Advances in Computer Systems Architecture Lecture Notes in Computer Science, Vol. 4679, pp-290-303, 2007.
8 Hennessy. J.L, Patterson. D.A, "Computer Archtiecture - A Quantitative Approach," Morgan Kaufmann, SanFrancisco, 2006.