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Automatic Layout Decomposition for DPT  

Moon, Dong-Sun (Electric Engineering and Computer Science, Hanyang University)
Shin, Hyun-Chul (Electric Engineering and Computer Science, Hanyang University)
Shin, Jae-Pil (Samsung Electronics co., Ltd.)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.4, 2008 , pp. 124-130 More about this Journal
Abstract
Automatic layout decomposition techniques have been developed for double patterning technology (DPT). As CMOS manufacturing process scales down to 45nm and below, lithography resolution needs to be improved. DPT has been proposed to enhance the limitation of conventional lithography, by decomposing the layout design into two masks to relax the minimum spacing requirement. However, it is not always possible to decompose a layout into two masks. We have developed new automatic stitching techniques to resolve this problem. Experimental results show that the suggested techniques are promising in decomposing layouts for DPT.
Keywords
Decomposing; Double Patterning Technology; Lithography;
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  • Reference
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