Browse > Article

A Power Efficient Versatile Carry Skip Adder Architecture for the Multimode Mobile Modem  

Han, Tae-Hee (School of Information and Communication Engineering, Sungkyunkwan University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.3, 2008 , pp. 86-93 More about this Journal
Abstract
The multi-mode terminal modem which is capable of accommodating a variety of wireless communication standards needs versatile arithmetic units for processing a variety of word lengths and wide range of data rates. Since the target hardware is usually designed to meet the required highest performance, it is often wasteful in power consumption especially when low rate data processing cases. Thus, a speed and power adaptability of the arithmetic unit is a desirable feature for the wireless applications. In this paper, we propose a power efficient versatile adder architecture with carry skip logic as a basic building block constructed in hierarchical manner. The validity of the architecture is shown with respect to size, performance, and power efficiency in diverse operating modes.
Keywords
power efficient; multimode modem; carry skip adder; hierarchical structure;
Citations & Related Records
연도 인용수 순위
  • Reference
1 On-line: http://www.sdrforum.org
2 C. Nagendra, M. J. Irwin, and R. M. Owens, "Area-time-power tradeoffs in parallel adders," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 53, no. 10, pp 689-702, October 1996
3 F. Kashifi, and N. Masoumi, "Optimization of Speed and Power in a 16-bit Carry Skip Adder in 70nm Technology," Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems, pp. 28-31, Aug. 2006
4 V. Kantabutra, "Designing optimum one-level carry-skip adders," IEEE Trans. on Computers, vol. 42, no. 6, pp. 759-764, June 1993   DOI   ScienceOn
5 M. Alioto and G. Palumbo, "A simple strategy for optimized design of one-level carry-skip adders," IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 50, no. 1, pp. 141-148, January 2003   DOI   ScienceOn
6 G. Panneerselvam, and B. Nowrouzian, "Multiply-add fused RISC architectures for DSP applications," Proceedings of the IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, pp 108 - 111, May 1993
7 A. Chandrakasan, S. Sheng, and R. Brodersen, "Low-power CMOS digital design," IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 473-484, Apr. 1992   DOI   ScienceOn
8 J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, 2nd ed. Upper Saddle River, NJ: Prentice-Hall, Dec. 2002
9 S. Turrini, "Optimum group distribution in carry-skip adders," in Proceedings of the 9th IEEE Symposium on Computer Arithmetic, pp. 96-103, Sep. 1989
10 A. Chandrakasan and R. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, Apr. 1995   DOI   ScienceOn
11 P. Chan, M. Schlag, C. Thomborson, and V. Oklobdzija, "Delay optimization of carry-skip adders and block carry-lookahead adders using multidimensional dynamic programming," IEEE Trans. on Computers, vol. 41, no. 8, pp. 920-930, Aug. 1992   DOI   ScienceOn
12 Y. S. Lin and D. Radhakrishnan, "Delay Efficient 32-bit Carry-Skip Adder," Proceedings of the 13th IEEE ICECS, pp. 506-509, Dec. 2006
13 TSMC 0.18um Process 1.8V SAGE-X Standard Cell Databook, Rel. 4.1, Artisan Component Inc., Sep. 2003