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Buffered Routing Tree Construction under Buffer Location and Wiring Constraints  

정동식 (삼성전자)
김덕환 (서강대학교 컴퓨터학과)
임종석 (서강대학교 컴퓨터학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.11, 2003 , pp. 73-82 More about this Journal
Abstract
In this paper, a simultaneous buffer insertion and routing method is proposed under the constraints of wire and buffer locations by macro or IP blocks. A new grid graph is proposed to describe the regions in which buffers(or both wires and buffers) are not available. Under this grid we describe a method of constructing a buffeted tree that minimize the maximum source to sink delay. The method is based on the dynamic programming with pruning unnecessary partial solutions. The proposed method improved the slack time of the delay by 19% on the average while using less buffers and similar wire length.
Keywords
buffer insertion; routing constraints performance driven ronting;
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1 L. P.P.P. van Ginneken, 'Buffer Placement in Distributed RC-tree Networks for Minimal Elmtore Delay,' Proc. ISCAS, 1990, pp. 865-868   DOI
2 C.J. Alpert, et al., 'Buffered Steiner Trees for Difficult Instances,' Proc. of ISPD, 2001, pp. 4-9   DOI
3 J. Hu et al., 'Buffer Insertion with Adap- tive Blockage Avoidance,' Proc. ISPD, 2002, pp. 92-97   DOI
4 T. Okamoto and J. Cong, 'Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization,' Proc. of ICCAD, 1996, pp. 44-49   DOI
5 J. Cong and X. Yuan, 'Routing Tree Construction Under Fixed Buffer Location,' Proc. of DAC, 2000, pp. 379-384   DOI
6 H. Zhou et al., 'Simultaneous Routing and Buffer Insertion with Restricts on Buffer Locations,' IEEE TCAD, Vol. 19, No. 7, pp. 819-824, July 2000   DOI   ScienceOn
7 J. Cong, et al., 'Efficient Algorithms for the Minimum Shortest Path Steiner Arbore- scence Problem with Applications to VLSI Physical Design,' IEEE TCAD, Vol. 17, No. 1, pp. 24-39, January 1998
8 C.J. Alpert and A. Devgan, 'Wire Segmenting for Improved Buffer Insertion,' Proc. of DAC, 1997, pp. 588-593
9 C.J. Alpert, et al., 'Steiner Tree Optimization for Buffers, Blockages, and Bays,' IEEE TCAD, Vol. 20, No. 4, pp. 556-562, Apr. 2001   DOI   ScienceOn
10 C.J. Alpert, et al., 'A Practical Metho- dology for Early Buffer and Wire Resource Allocation,' Proc. of DAC, 2001, pp. 189-194
11 W.C. Elmore, 'The Transient Response of Damped Linear Network with Particular Regard to Wideband Amplifier,' J. Applied Physics, pp. 55-63, 1948   DOI