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Topography Modeling and Simulation for the Complex Structures of ULSI Interconnects  

Gwon, O-Seop (인하대학교 공과대학 전자전기공학부 컴퓨테이셔녈 일렉트로닉스 센터)
Yun, Seok-In (인하대학교 공과대학 전자전기공학부 컴퓨테이셔녈 일렉트로닉스 센터)
Kim, Yun-Tae (인하대학교 공과대학 전자전기공학부 컴퓨테이셔녈 일렉트로닉스 센터)
Yun, Im-Dae (인하대학교 공과대학 전자전기공학부 컴퓨테이셔녈 일렉트로닉스 센터)
Won, Tae-Yeong (인하대학교 공과대학 전자전기공학부 컴퓨테이셔녈 일렉트로닉스 센터)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.4, 2002 , pp. 26-34 More about this Journal
Abstract
A dynamically-allocated topographical model, so-called cell advancing model, has been developed modifying the cell model. Memory requirements are reduced by dynamically allocating completed topography and material information only at surface cells, and setting other cells as a material index. In this paper, this model is presented and verified with applications to etching process by using the analytic model and Monte Carlo model for the incident ion flux, deposition process, and process integration. In case of DRAM cell fabrication process with 5,440,500(130$\times$155$\times$270) cells takes about 22MB memory to represent the topography.
Keywords
cell advancing model; etching; deposition, topography; process simulation;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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