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Fast Multi-Phase Packet Classification Architecture using Internal Buffer and Single Entry Caching  

Kang, Dae-In (Department of Electrical and Electronic Engineering, Yonsei University)
Park, Hyun-Tae (Department of Electrical and Electronic Engineering, Yonsei University)
Kim, Hyun-Sik (Department of Electrical and Electronic Engineering, Yonsei University)
Kang, Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea TC / v.44, no.9, 2007 , pp. 38-45 More about this Journal
Abstract
With the emergence of new applications, packet classification is essential for supporting advanced internet applications, such as network security and QoS provisioning. As the packet classification on multiple-fields is a difficult and time consuming problem, internet routers need to classify incoming packet quickly into flows. In this paper, we present multi-phase packet classification architecture using an internal buffer for fast packet processing. Using internal buffer between address pair searching phase and remained fields searching phases, we can hide latency from the characteristic that search times of source and destination header fields are different. Moreover we guarantee the improvement by using single entry caching. The proposed architecture is easy to apply to different needs owing to its simplicity and generality.
Keywords
Packet Classification; Internal Buffer; Multi-Phase Search; Parallel Search; Caching;
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