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Design of a PLL Frequency Synthesizer for RSSI Applications Using Phase Noise Analysis  

Kim, Nam-Tae (Dept. of Electronic Eng., Inje University)
Jeong, Jae-Han (KDC R&D, Ethertronics Inc.)
Song, Han-Jung (Dept. of Nano Eng., Inje University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea TC / v.48, no.12, 2011 , pp. 28-34 More about this Journal
Abstract
In this paper, a PLL frequency synthesizer for RSSI applications is designed by phase noise analysis. Required synthesizer performance is achieved by optimizing the noise performance of PLL components and a loop transfer function, since its phase noise, lock time, and spur suppression capability are determined by the performance of loop components and loop filter characteristics. As an application example, a PLL frequency synthesizer for RSSI applications, which operates at the frequency of 2.288GHz, is designed using the phase noise analysis. The validity of the design technique is proved by experiments.
Keywords
phase-locked loop; frequency synthesizer; phase noise; RSSI;
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