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High Performance 32-bit Embedded AES for Wireless Network Router Applications  

Lin, Deng (School of Information and Communication Engineering, Chungbuk National University)
You, Young-Gap (College of Electrical and Computer Engineering, Chungbuk National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea TC / v.47, no.11, 2010 , pp. 97-104 More about this Journal
Abstract
This paper presents a high performance 32-bit single core AES architecture. The proposed architecture employs a 5-stage pipeline: four stages in the ShiftRows/InvShiftRows module, and one stage in the MixColumn/InvMixColumn module. Circuit size reduction has been achieved through merging of the shift rows and inverse shift rows. The mix column and inverse mix column share the same resources. Three 32-bit registers replace the conventional ten 32-bit registers in the RCON architecture. The proposed architecture has been implemented in Verilog HDL, and yields 415 Mbits/s throughput with the circuit size of 13764 gate equivalents on the 0.18um CMOS process technology. This high performance architecture is suitable for wireless network router applications.
Keywords
AES; high performance; single core; pipeline; wireless network router;
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Times Cited By KSCI : 2  (Citation Analysis)
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