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Memory Reduction of IFFT Using Combined Integer Mapping for OFDM Transmitters  

Lee, Jae-Kyung (Div. of Electronic & Information Engineering, Information & Telecommunications Research Center, Chonbuk National University)
Jang, In-Gul (Div. of Electronic & Information Engineering, Information & Telecommunications Research Center, Chonbuk National University)
Chung, Jin-Gyun (Div. of Electronic & Information Engineering, Information & Telecommunications Research Center, Chonbuk National University)
Lee, Chul-Dong (KETI)
Publication Information
Journal of the Institute of Electronics Engineers of Korea TC / v.47, no.10, 2010 , pp. 36-42 More about this Journal
Abstract
FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically $log_2N$) as the FFT point-size (N) increases, the number of required registers (or, memories) increases linearly. In large point-size FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 38.5% area reduction compared with previous IFFT designs.
Keywords
IFFT; Integer mapping; Quantization; Memory reduction; Cognitive radio;
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