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The viterbi decoder implementation with efficient structure for real-time Coded Orthogonal Frequency Division Multiplexing  

Hwang Jong-Hee (Dept. of Information and Communication Engineering, Inha University)
Lee Seung-Yerl (Dept. of Information and Communication Engineering, Inha University)
Kim Dong-Sun (Korea Electronic Technology Institute)
Chung Duck-Jin (Dept. of Information and Communication Engineering, Inha University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea TC / v.42, no.2, 2005 , pp. 61-74 More about this Journal
Abstract
Digital Multimedia Broadcasting(DMB) is a reliable multi-service system for reception by mobile and portable receivers. DMB system allows interference-free reception under the conditions of multipath propagation and transmission errors using COFDM modulation scheme, simultaneously, needs powerful channel error's correction ability. Viterbi Decoder for DMB receiver uses punctured convolutional code and needs lots of computations for real-time operation. So, it is desired to design a high speed and low-power hardware scheme for Viterbi decoder. This paper proposes a combined add-compare-select(ACS) and path metric normalization(PMN) unit for computation power. The proposed PMN architecture reduces the problem of the critical path by applying fixed value for selection algorithm due to the comparison tree which has a weak point from structure with the high-speed operation. The proposed ACS uses the decomposition and the pre-computation technique for reducing the complicated degree of the adder, the comparator and multiplexer. According to a simulation result, reduction of area $3.78\%$, power consumption $12.22\%$, maximum gate delay $23.80\%$ occurred from punctured viterbi decoder for DMB system.
Keywords
Digital Multimedia Broadcasting (DMB); Viterbi Decoder(VD); Branch Metric (BM); Path Metric Normalization(PMN); Add-Compare-Select(ACS); Trace-Back(TB);
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