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Design of a High-speed Decision Feedback Equalizer using the Constant-Modulus Algorithm  

Jeon, Yeong-Seop (삼성전자 통신연구소)
Kim, Gyeong-Ho (아주대학교 공과대학 전자공학부)
Publication Information
Journal of the Institute of Electronics Engineers of Korea TC / v.39, no.4, 2002 , pp. 173-179 More about this Journal
Abstract
This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. The DFE structure has better channel adaptive performance and lower BER than the transversal structure. The proposed equalizer can be used for 16/64 QAM modems. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL filter. The proposed equalizer shows low BER in multipath fading channel. We have performed models. From the simulation results, we employ a 12 tap feedback filter and a 8 tap feedforward logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5$\mu\textrm{m}$ standard cell library (STD80) and verified function and timing simulations. The total number of gates is about 130,000.
Keywords
QAM; QPSK;
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